The present invention relates to a semiconductor device including a field effect transistor, and more particularly relates to an improved semiconductor device in which the mobility of carriers is increased by applying a tensile strain to a channel layer where carriers are moving.
Currently, the majority of transistors formed on a silicon substrate are metal-insulator-semiconductor (MIS) field effect transistors. Methods for enhancing the performance characteristics of an MIS transistor by applying a tensile strain to an Si channel layer were reported by J. Welser et al. in xe2x80x9cStrain Dependence of the Performance Enhancement in Strained-Si n-MOSFETsxe2x80x9d, IEDM Tech. Dig. 1994, p. 373, and by K. Rim et al. in xe2x80x9cEnhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETsxe2x80x9d, IEDM Tech. Dig. 1995, p. 517.
FIG. 16 is a cross-sectional view illustrating a basic structure of a semiconductor region in a field effect transistor formed by these methods. As shown in FIG. 16, the semiconductor region basically includes: an SiGe buffer layer 101, in which the content of Ge linearly increases from 0 to x; an Sil-xGex layer 102, the lattice strain of which has been relaxed; and an Si layer 103, which has received a tensile strain. These layers are stacked in this order on a silicon substrate 100. In this structure, the lattice strain of the Sil-xGe, layer 102, formed on the SiGe buffer layer 101, is relaxed such that the lattice constant of the Sil-xGex layer 102 increases to match with that of the non-strained SiGe layer 101. And a tensile strain is applied to the Si layer 103 grown thereon.
FIG. 17(a) is a crystal structure diagram illustrating the lattice states of an Sil-xGex layer and an Si layer before these layers are stacked one upon the other. FIG. 17(b) is a crystal structure diagram illustrating a state where the Si layer has received a tensile strain after these layers have been stacked. And FIG. 17(c) is a band diagram illustrating a heterojunction structure consisting of the Sil-xGex layer and the Si layer. As shown in FIG. 17(a), the lattice constant of Si crystals is smaller than that of Sil-xGex crystals. Thus, if the Si layer is epitaxially grown on the Sil-xGex layer, the Si layer receives a tensile strain from the Sil-xGex layer as shown in FIG. 17(b). As a result, the energy band of the heterojunction structure consisting of the Sil-xGex layer and the Si layer, which has received the tensile strain, is as shown in FIG. 17(c). Specifically, since the Si layer has received a tensile strain, the sixfold degeneracy is dissolved in the conduction band, which is split into a twofold degenerate band xcex94(2) and a fourfold degenerate band xcex94(4). On the other hand, the twofold degeneracy is also dissolved in the valence band, which is split into a light-hole band LH and a heavy-hole band HH.
That is to say, in such a heterojunction structure, the edge of the conduction band in the Si layer 103 shown in FIG. 16 is the twofold degenerate band xcex94(2), and has smaller energy than that of electrons in the Sil-xGex layer 102. Thus, if a field effect transistor is formed by using the Si layer 103 as a channel, then electrons, having a smaller effective mass in the band xcex94(2), move through the channel. As a result, the horizontal mobility of electrons increases in the Si layer 103 and the operating speed of the transistor also increases. In addition, the energy level of the band xcex94(2) is lower than that at the edge of the conduction band in the Sil-xGex layer 102. Thus, if the Si layer 103 is used as a channel, electrons can be confined in the Si layer by utilizing a heterobarrier formed between the Si and Sil-xGex layers.
On the other hand, the edge of the valence band of the Si layer 103 is a band of light holes having a smaller effective mass, which have smaller energy than that of holes in the Sil-xGex layer 102. Thus, if such an Si layer 103 is used as a channel region for a p-channel transistor, then the light holes, having a smaller effective mass, horizontally move in the Si layer 103. As a result, the mobility of holes increases and the operating speed of the transistor also increases.
As reported, in both n- and p-channel field effect transistors, the performance characteristics thereof can be enhanced by using an Si layer 103, which has received a tensile strain, as a channel region.
However, these field effect transistors, formed by the conventional methods, have the following problems.
Firstly, in order to apply a tensile strain to the Si layer 103 functioning as a channel region, the SiGe buffer layer 101 should be grown on the silicon substrate 100 until the layer 103 becomes thick enough to reduce the lattice strain of the Sil-xGex layer 102. However, when the lattice strain of the Sil-xGex layer 102 is relaxed, a large number of dislocation are generated in the SiGe buffer layer 101. A great number of dislocations are also present in the Si layer 103 formed on the Sil-xGex layer 102. The dislocations such as these not only deteriorate the performance characteristics of the transistor, but also seriously affect the long-term reliability thereof. For example, it was reported that the dislocations could be reduced by modifying the structure of the SiGe buffer layer. However, in accordance with current techniques, the density of dislocations cannot be reduced to lower than about 105 cmxe2x88x922. Such a device must be said to have very many defects.
Secondly, the buffer layer, provided for reducing the lattice strain, should be formed sufficiently thick (e.g., 1 xcexcm or more). Thus, it takes a great deal of time to form such a layer by crystal growth. In view of the throughput of a device, such a structure is far from fully practical.
Thirdly, in the conventional structure, the energy level at the edge of the valence band in the Si layer 103 is lower than the energy level at the edge of the valence band in the Sil-xGex layer 102. Thus, a heterobarrier, where the Sil-xGex layer 102 is located at a higher level, is formed, and it cannot be expected that holes, having a smaller effective mass, are confined in the Si layer 103.
In view of these problems, the present invention was made to provide a sufficiently reliable, high-performance transistor by applying a tensile strain to a channel layer mainly composed of silicon, without providing any thick buffer layer for reducing a lattice strain, in which a large number of dislocations exist.
The semiconductor device of the present invention includes a field effect transistor on a substrate. The field effect transistor includes: a first silicon layer formed on the substrate; a second silicon layer, which is formed on the first silicon layer, contains carbon and has received a tensile strain from the first silicon layer; and a gate electrode formed over the second silicon layer. The second silicon layer functions as a channel region of the field effect transistor.
In this semiconductor device, since carbon, having a smaller atomic diameter than that of silicon, is contained in the second silicon layer, the lattice constant of the second silicon layer is smaller than that of the first silicon layer. Accordingly, even if no thick buffer layer is provided between the first and second silicon layers, the second silicon layer containing carbon receives a tensile strain from the first silicon layer. As a result, in the second silicon layer, the sixfold degeneracy is dissolved in the conduction band, which is split into a twofold degenerate band and a fourfold degenerate band. The edge of the conduction band in the channel region formed out of the second silicon layer is the twofold degenerate band. The effective mass of twofold degenerate electrons is smaller than that of electrons in the first silicon layer. Thus, if current is horizontally supplied, the effective mass of electrons decreases on the plane and the mobility of electrons increases. In addition, since the distance between these two split bands is greater, the scattering between the valleys of these bands can be suppressed. Accordingly, the mobility of electrons further increases. As a result, the operating speed of a field effect transistor, including an n-channel where electrons move, increases. Also, the energy level of the twofold degenerate band in the second silicon layer is lower than that at the edge of the conduction band in the first silicon layer. Thus, in this structure, electrons can be confined in the second silicon layer by the heterobarrier formed between the first and second silicon layers.
On the other hand, in the second silicon layer, the degeneracy is also dissolved in the valence band, which is split into a light-hole band and a heavy-hole band. The edge of the valence band in the channel region formed out of the second silicon layer is the band consisting of light holes having a smaller effective mass. The effective mass of the light holes is smaller than that of holes in the first silicon layer. Thus, in a field effect transistor having a p-channel where holes move, the effective mass of holes decreases and the mobility of holes increases. As a result, the operating speed of the transistor increases.
Also, the energy level of the light-hole band is higher than that at the edge of the valence band in the first silicon layer. Thus, in this structure, light holes can be confined in the second silicon layer by a heterobarrier-formed between the first and second silicon layers.
Furthermore, since the second silicon layer does not have to be thick, a crystal layer having almost no dislocations can be easily formed by controlling the thickness at a critical thickness thereof or less, for example. Moreover, since no thick buffer layer is required for reducing the lattice strain, the throughput can also be increased. Accordingly, a highly reliable, high-performance semiconductor device functioning as a field effect transistor can be obtained at a lower cost.
In one embodiment of the present invention, if the field effect transistor is an n-channel field effect transistor, the second silicon layer is an n-channel where electrons move.
In another embodiment of the present invention, electrons are preferably confined by a heterobarrier formed between the first and second silicon layers of the n-channel field effect transistor.
In such an embodiment, a field effect transistor, in which electrons can be confined by the heterobarrier more efficiently, is obtained.
In still another embodiment, the semiconductor device preferably further includes a heavily doped layer, which is formed in the first silicon layer in the vicinity of the second silicon layer and contains a high-concentration n-type dopant.
In such an embodiment, the heavily doped layer for supplying carriers is spatially separated from the channel functioning as a carrier-accumulating layer. Thus, the carriers, moving through the channel, are not scattered by the ionized impurities, and therefore can move at a high velocity.
In still another embodiment, it is more preferable that the second silicon layer is a quantum well.
In such an embodiment, carriers, which have been induced in the second silicon layer functioning as a channel region, are confined in the quantum well and do not get over the heterobarrier even when the carrier density is high. As a result, the carriers move stably.
In still another embodiment, the semiconductor device may further include a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer. Electrons may be confined in the second silicon layer by a potential well formed in a boundary between the second and third silicon layers.
In such an embodiment, a channel where electrons move exists under the third silicon layer, not under the gate insulating film. Accordingly, the electrons, moving through the channel, are hardly scattered by an interface level existing in the interface between the gate insulating film and the third silicon layer or by the roughness of the interface. As a result, a higher operating speed is ensured as compared with a general MOS transistor.
In this case, the semiconductor device preferably further includes a heavily doped layer, which is formed in the third silicon layer in the vicinity of the second silicon layer and contains a high-concentration n-type dopant.
In still another embodiment, the semiconductor device may further include a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer. Electrons may be confined in the second silicon layer by a heterobarrier formed between the first and second silicon layers and another heterobarrier formed between the second and third silicon layers.
In such an embodiment, a heterobarrier is also formed between the second and third silicon layers. Accordingly, electrons can be confined very efficiently in the second silicon layer interposed between the heterobarrier formed between the first and second silicon layers and the heterobarrier formed between the second and third silicon layers.
In still another embodiment, if the field effect transistor is a p-channel field effect transistor, the second silicon layer is a p-channel where holes move.
In this case, holes are preferably confined by a heterobarrier formed between the first and second silicon layers of the p-channel field effect transistor.
In such an embodiment, a field effect transistor, in which holes can be confined by the heterobarrier very efficiently, is obtained.
In still another embodiment, the semiconductor device preferably further includes a heavily doped layer, which is formed in the first silicon layer in the vicinity of the second silicon layer and contains a high-concentration p-type dopant.
In such an embodiment, the heavily doped layer for supplying carriers is spatially separated from the channel functioning as a carrier-accumulating layer. Thus, the carriers, moving through the channel, are not scattered by the ionized impurities, and therefore can move at a high velocity.
In the same way as the n-channel field effect transistor, it is more preferable that the second silicon layer is a quantum well.
In still another embodiment, the p-channel field effect transistor may further include a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer. Holes may be confined in the second silicon layer by a potential well formed in a boundary between the second and third silicon layers.
In this case, the semiconductor device preferably further includes a heavily doped layer, which is formed in the third silicon layer in the vicinity of the second silicon layer and contains a high-concentration p-type dopant.
In still another embodiment, the p-channel field effect transistor may further include a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer. Holes may be confined in the second silicon layer by a heterobarrier formed between the first and second silicon layers and another heterobarrier formed between the second and third silicon layers.
In these three embodiments, the same effects as those described above are attained, whereby a field effect transistor, in which holes can be confined very efficiently, is obtained.
In still another embodiment, the semiconductor device preferably further includes a gate insulating film formed just under the gate electrode.
In still another embodiment, the thickness of the second silicon layer is preferably smaller than a critical thickness, which is determined by the composition of carbon and above which dislocations are generated.
In such an embodiment, the second silicon layer may be composed of crystals having no dislocations and excellent crystallinity. Thus, it is possible to prevent the electrical characteristics of a field effect transistor from being deteriorated owing to the existence of high-density dislocations.
In still another embodiment, the second silicon layer may further contain germanium.
In such an embodiment, carbon, having a smaller atomic diameter than that of silicon, is contained together with germanium in the second silicon layer. Thus, if the compositions of carbon and germanium are adjusted, it is easy to set the lattice constant of the second silicon layer at a value smaller than that of the first silicon layer. Accordingly, even if no thick buffer layer is provided between the first and second silicon layers, the second silicon layer can receive a tensile strain from the first silicon layer. As a result, the above effects can be attained. In addition, the following effects can also be attained.
Specifically, the energy level difference between the light-hole band in the second silicon layer, containing carbon and germanium and having received a tensile strain, and the edge of the valence band in the first silicon layer is larger than the energy level difference between the light-hole band in the second silicon layer, containing carbon and having received a tensile strain, and the edge of the valence band in the first silicon layer. Thus, holes are expectedly confined more effectively. In addition, by changing the compositions of germanium and carbon, the heights of the heterobarriers at the edges of the valence band and the conduction band can be appropriately controlled depending on the type of the semiconductor device and so on.
In still another embodiment, the field effect transistor is an n-channel field effect transistor in which the second silicon layer is an n-channel. The semiconductor device further includes a p-channel field effect transistor. The p-channel field effect transistor includes: a fourth silicon layer formed on the substrate; a fifth silicon layer, which is formed on the fourth silicon layer, contains carbon and has received a tensile strain from the fourth silicon layer; and a gate electrode formed over the fifth silicon layer. The fifth silicon layer functions as a p-channel region. In this structure, the semiconductor device can function as a complementary device.
In such an embodiment, a p-channel field effect transistor including a p-channel, where the mobility of holes is high, and an n-channel field effect transistor including an n-channel, where the mobility of electrons is high, can be formed by using a multilayer film in common. In a conventional semiconductor device, a channel region functioning only as a p-channel, where the mobility of holes is high, and another channel region functioning only as an n-channel, where the mobility of electrons is high, should be stacked one upon the other. In such a case, in one of the channel regions, sufficient field effects cannot be attained, because the channel region is more distant from the gate electrode. In the structure of the present invention, however, such an inconvenience can be avoided.
In still another embodiment of the semiconductor device functioning as a complementary device, carbon contained in the second silicon layer of the n-channel field effect transistor preferably has an equal composition to that of carbon contained in the fifth silicon layer of the p-channel field effect transistor.
In such an embodiment, the second silicon layer of the n-channel field effect transistor and the fifth silicon layer of the p-channel field effect transistor can be formed during the same growth process step. As a result, the fabrication process can be simplified and the fabrication costs can be further cut down.
In still another embodiment, the semiconductor device functioning as a complementary device preferably further includes a gate insulating film formed just under the gate electrode. And the thickness of the fifth silicon layer is preferably smaller than a critical thickness, which is determined by the composition of carbon and above which dislocations are generated.
In still another embodiment, the second and fifth silicon layers may further contain germanium.
In such an embodiment, by changing the compositions of germanium and carbon, the heights of the heterobarriers at the edges of the valence band and the conduction band can be appropriately controlled depending on the type of the semi-conductor device and so on. Thus, a channel that can confine carriers with high efficiency can be formed by using the same structure in common, no matter whether the channel is n-type or p-type.
In this case, germanium contained in the second silicon layer preferably has an equal composition to that of germanium contained in the fifth silicon layer.
In such an embodiment, the second silicon layer of the n-channel field effect transistor and the fifth silicon layer of the p-channel field effect transistor can be formed during the same growth process step. As a result, the fabrication process can be simplified and the fabrication costs can be further cut down.